1. Field of the Invention
This invention relates to semiconductor device manufacturing and, more particularly, to an improved manufacturing method for reducing gate induced drain leakage (GIDL) within MOSFETs.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Current trends within integrated circuit technologies involve reducing the feature dimensions within integrated circuits to increase performance. For instance, the length, width and (sometimes) depth of various features within a metal oxide semiconductor field effect transistor (MOSFET) may be reduced to increase performance and the density of integration within a semiconductor device. In one application, scaling down features within random access memories has allowed cell sizes to shrink, in effect enabling larger memory sizes, lower cost per bit and improved speed.
However, the continuous scaling of feature dimensions has led to shorter and shorter channel lengths within MOS transistors. As described in more detail below, a short channel length may cause significant current leakage between the gate and drain regions of the MOSFET, even though a voltage lower than the threshold voltage is applied to the gate of the MOSFET. A high current leakage leads to high power consumption in the standby condition, and thus, is very undesirable.
One approach for fabricating a MOSFET is shown in FIG. 1. In particular, FIG. 1 depicts a partial cross-sectional view of semiconductor topography 100 in which a pair of gate structures 110a and 110b are patterned upon semiconductor layer 120. As is known in the art, semiconductor layer 120 may be doped n-type, p-type or both. For example, semiconductor layer 120 may be doped n-type to form PMOS transistors or p-type to form NMOS transistors. In addition, semiconductor layer 120 may include isolation regions 130. Although not shown, an isolation region may also be interposed between the gate structures. For example, an isolation region may be interposed between gate structures 110a and 110b to form a pair of CMOS transistors. In such an embodiment, one side of the isolation region may be doped n-type to form a PMOS transistor, while the other side is doped p-type to form an NMOS transistor.
In general, the gate structures may be formed by patterning one or more layers. For example, the gate structures may be formed by depositing and patterning one or more conductive materials 114, such as doped amorphous silicon, doped polysilicon, titanium, tungsten, or any metal alloy, nitride or silicide thereof. In some embodiments, the gate structures may include a dielectric cap material 116 to isolate the conductive material(s) 114 from overlying layers and structures. In addition, the gate structures may include a gate dielectric layer 112 interposed between the conductive material(s) 114 and semiconductor layer 120. The gate dielectrics and cap layers may be composed of the same or different materials and may generally include one or more dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride, or other dielectric materials with a relatively high dielectric constant.
Next, dielectric sidewall spacers 118 may be formed upon the sidewall surfaces of the gate structures. The dielectric sidewall spacers 118 may be used to form graded junctions (i.e., active areas) within the substrate on opposite sides of a gate structure. In most cases, graded junctions are formed by first implanting a light concentration of dopant self-aligned to the sidewall surfaces of the gate structure prior to forming the dielectric sidewall spacers. After the sidewall spacers are formed, a heavier concentration of dopant self-aligned to the outer lateral surfaces of the spacers may be forwarded into the substrate. The purpose of the first implant is to produce lightly doped source/drain regions 140 within the substrate. These lightly doped diffusion regions straddle a channel region 150 formed directly underneath the gate structure. The second implant forms heavily doped source/drain regions 160 within the substrate. Together, the lightly doped 140 and heavily doped 160 source/drain regions form graded junctions, which increase in dopant concentration in a lateral direction away from the gate structure. As shown in FIG. 1, the heavily doped source/drain regions 160 may be laterally spaced from the channel region 150 by a distance, which is dictated by the thickness of the sidewall spacer 118 and the diffusion length.
After the dopant implants, the semiconductor topography 100 may be annealed to activate the dopants within the source/drain regions. In many cases, the anneal process includes a rapid thermal anneal (RTA) process in which the semiconductor topography is exposed to relatively high temperatures for a short period of time, such as between approximately 800° C. and approximately 1100° C. for less than a minute and, in some cases, for approximately 20 seconds. However, the RTA process may increase the diffusion of the source and drain regions, causing the regions to extend wider and deeper than allowed by the design specifications of the ensuing device, particularly as feature dimensions are scaled down for newer technologies.
In some cases, a relatively short distance may exist between the gate and the source/drain diffusion regions of a subsequently formed MOSFET. The relatively short distance may introduce a significant leakage current between the gate and drain regions of the MOSFET. In other words, a tunneling current may be generated between the drain region and its adjacent channel region even when the MOSFET is in an “off” state. This tunneling current is referred to as gate induced drain leakage (GIDL) and is typically dependent on the amount of gate/drain overlap (i.e., the amount of overlap capacitance) within the MOSFET device. Large GIDL currents increase the current consumption of the MOSFET in standby mode and may even cause premature transistor breakdown, which leads to low yield.
Several methods have been proposed to reduce the amount of gate induced drain leakage (GIDL) within a MOS transistor. For example, methods have been proposed to increase the thickness of the gate dielectric layer, increase the width of the dielectric sidewall spacers and/or change the concentration of the channel or source/drain implantations. However, these methods tend to change the threshold voltage, violate design rules or increase the overall size of the MOS transistor. In addition, these methods cannot be used to reduce the gate/drain overlap without effecting nearby transistors.
Therefore, a need remains for an improved semiconductor topography and method for reducing gate induced drain leakage (GIDL) within a MOS transistor. Preferably, an improved semiconductor topography and method in accordance with the present invention will reduce GIDL in a MOS transistor while overcoming the disadvantages of conventional methods.